A variety of electronic and computer systems include a reset function for resetting a memory array to a predetermined state, usually all zeros. Typical applications requiring a reset function are cache tag memories, cache memory, video display memories, and writable control storage.
The basic operation of a reset function is that the system generates a reset signal, and that reset signal is used to activate internal circuitry that causes all of the memory cells in a memory device or array to switch to a predetermined state.
FIG. 1 shows a standard six transistor CMOS static memory cell 10 having two cross-coupled CMOS inverters T1-T2 and T3-T4, and access control transistors T5 and T6 which couple the cell 10 to bit lines BL and BL. Each CMOS inverter has a P-channel transistor T1 or T3 with its source coupled to Vcc, the high voltage power supply for the memory, and its drain coupled to an N-channel transistor T2 or T4. The sources of the N-channel transistors T2 and T4 are coupled to Vss, the lower voltage power supply for the memory, also called the ground node.
The prior art includes SRAM devices having reset functions in which the device responds to a reset signal by setting all of the bit lines BL and BL to a predetermined state (e.g., BL=0 and BL=1), and then activating all of the word lines in the device. This causes the bit value on the bit lines to be written simultaneously into all of the memory cells in the device.
One of the major draw backs of this approach to resetting a memory array is that all of the memory cells in the array which switch value will draw current at the same time. Furthermore, additional power will be consumed by the drivers for the bit lines and the drivers for the word lines. Thus, the reset function is likely to be the cause of the largest single current spike incurred by the memory device.
It would be possible to reduce the current spike associated with the reset function by splitting the memory array into two or more sections, and separately resetting each section by selecting the corresponding word lines after setting the bit lines to their predetermined states. While this will reduce the magnitude of the current spike associated with resetting the memory, it also increases the amount of time it takes to reset all of the cells in the memory device--which is not desirable In addition, this method of resetting a memory array may require a "reset recovery time" before the memory can be accessed, much like the "write recovery time" required by some memory devices after data is written into the device.
In general, the inventors have concluded that this prior art approach to memory reset is not practical for high density memories, particularly for memory devices with array sizes of 64k and larger, because the current spike caused by the reset function would be excessive.
Another prior art technique for resetting static memory devices, shown in FIG. 2, requires the addition of a reset transistor TR to every cell 15 in the memory. This has the obvious disadvantage of increasing the size of the memory cell and thus the size of the entire memory device. Furthermore, the reset transistor TR causes the memory cell to be nonsymmetric and upsets the capacitive balance of the memory cell 15, which can be compensated for, but is generally undesirable.
It is therefore an object of the present invention to provide a memory reset apparatus and method which minimizes the current spike problems associated with the first prior approach discussed above, and which does not increase the size of the memory cell.
Another object of the present invention is to provide a memory reset apparatus and method which is both very fast, and uses a relatively small amount of power.